Vicent Canals

Publication Activity (10 Years)

Years Active: 2004-2022
Publications (10 Years): 5

Top Topics

Statistical Pattern Recognition

Hardware Implementation

Top Venues

Integr. Comput. Aided Eng.

IEEE Trans. Neural Networks Learn. Syst.

Publications

Josep L. Rosselló, Joan Font-Rosselló, Christiam F. Frasser, Alejandro Morán, Erik S. Skibinsky-Gitlin, Vicent Canals, Miquel Roca
Hardware Implementation of Stochastic Computing-based Morphological Neural Systems. ISCAS (2022)
Christiam F. Frasser, Pablo Linares-Serrano, Alejandro Morán, Joan Font-Rosselló, Vicent Canals, Miquel Roca, Teresa Serrano-Gotarredona, Josep L. Rosselló
Exploiting Correlation in Stochastic Computing based Deep Neural Networks. DCIS (2021)
Christiam F. Frasser, Pablo Linares-Serrano, Vicent Canals, Miquel Roca, Teresa Serrano-Gotarredona, Josep L. Rosselló
Fully-parallel Convolutional Neural Network Hardware. CoRR (2020)
Antoni Morro, Vicent Canals, Antoni Oliver, Miquel L. Alomar, Fabio Galán-Prado, Pedro J. Ballester, José Luis Rosselló
A Stochastic Spiking Neural Network for Virtual Screening. IEEE Trans. Neural Networks Learn. Syst. 29 (4) (2018)
Vicent Canals, Christiam F. Frasser, Miquel L. Alomar, Antoni Morro, Antoni Oliver, Miquel Roca, Eugeni Isern, Víctor Martínez-Moll, Eugeni García-Moreno, Josep L. Rosselló
Noise tolerant probabilistic logic for statistical pattern recognition applications. Integr. Comput. Aided Eng. 24 (4) (2017)
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
Stochastic Spiking Neural Networks at the EDGE of CHAOS. IJCNN (2014)
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing. Int. J. Neural Syst. 24 (5) (2014)
Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló
Low-cost hardware implementation of Reservoir Computers. PATMOS (2014)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs CoRR (2007)
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN (2006)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE (2005)
Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
A BIST-based Charge Analysis for Embedded Memories. IOLTS (2004)