José Luis Rosselló

Publication Activity (10 Years)

Years Active: 1998-2018
Publications (10 Years): 2

Top Topics

Hardware Implementation

Liquid State Machine

Virtual Screening

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

IEEE Trans. Neural Networks Learn. Syst.

Publications

Antoni Morro, Vicent Canals, Antoni Oliver, Miquel L. Alomar, Fabio Galán-Prado, Pedro J. Ballester, José Luis Rosselló
A Stochastic Spiking Neural Network for Virtual Screening. IEEE Trans. Neural Networks Learn. Syst. 29 (4) (2018)
Joan Barceló, José Luis Rosselló, Sebastià A. Bota, Jaume Segura, Jaume Verd
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective. Commun. Nonlinear Sci. Numer. Simul. 30 (Issues) (2016)
Miquel L. Alomar, Miguel C. Soriano, Miguel Angel Escalona-Moran, Vincent Canals, Ingo Fischer, Claudio R. Mirasso, José Luis Rosselló
Digital Implementation of a Single Dynamical Node Reservoir Computer. IEEE Trans. Circuits Syst. II Express Briefs (10) (2015)
Miquel L. Alomar, Vincent Canals, Víctor Martínez-Moll, José Luis Rosselló
Stochastic-Based Implementation of Reservoir Computers. IWANN (2) (2015)
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
Stochastic Spiking Neural Networks at the EDGE of CHAOS. IJCNN (2014)
José Luis Rosselló, Vicent Canals, Antoni Oliver, Antoni Morro
Studying the Role of Synchronized and Chaotic Spiking Neural Ensembles in Neural Information Processing. Int. J. Neural Syst. 24 (5) (2014)
Miquel L. Alomar, Vicent Canals, Víctor Martínez-Moll, José Luis Rosselló
Low-cost hardware implementation of Reservoir Computers. PATMOS (2014)
José Luis Rosselló, Vincent Canals, Antoni Morro
Probabilistic-based neural network implementation. IJCNN (2012)
José Luis Rosselló, Vincent Canals, Antoni Morro, Antoni Oliver
Hardware Implementation of Stochastic Spiking Neural Networks. Int. J. Neural Syst. 22 (4) (2012)
Vincent Canals, Antoni Morro, José Luis Rosselló
Stochastic-Based Pattern Recognition Analysis CoRR (2012)
José Luis Rosselló, Vincent Canals, Antoni Morro
Hardware implementation of stochastic-based Neural Networks. IJCNN (2010)
Vincent Canals, Antoni Morro, José Luis Rosselló
Stochastic-based pattern-recognition analysis. Pattern Recognit. Lett. 31 (15) (2010)
Gabriel Torrens, Bartomeu Alorda, Salvador Barcelo, José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination. IEEE Trans. Circuits Syst. II Express Briefs (4) (2010)
José Luis Rosselló, Vincent Canals, Antoni Morro, Jaume Verd
Chaos-Based Mixed Signal Implementation of Spiking Neurons. Int. J. Neural Syst. 19 (6) (2009)
José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. ICANN (1) (2009)
José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl
Practical Hardware Implementation of Self-configuring Neural Networks. ISNN (3) (2009)
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro
A simple CMOS chaotic integrated circuit. IEICE Electron. Express 5 (24) (2008)
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
Using stochastic logic for efficient pattern recognition analysis. IJCNN (2008)
José Luis Rosselló, Ivan de Paúl, Vincent Canals
Self-configuring spiking neural networks. IEICE Electron. Express 5 (22) (2008)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs CoRR (2007)
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs. DATE (2007)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs CoRR (2007)
Sebastià A. Bota, José Luis Rosselló, Carol de Benito, Ali Keshavarzi, Jaume Segura
Impact of Thermal Gradients on Clock Skew and Testing. IEEE Des. Test Comput. 23 (5) (2006)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Low V_D_D vs. Delay: Is it Really a Good Correlation Metric for Nanometer ICs?. VTS (2006)
José Luis Rosselló, Jaume Segura
A compact model to identify delay faults due to crosstalk. DATE (2006)
José Luis Rosselló, Carol de Benito, Sebastià A. Bota, Jaume Segura
Leakage Power Characterization Considering Process Variations. PATMOS (2006)
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN (2006)
José Luis Rosselló, Sebastià A. Bota, Jaume Segura
Compact Static Power Model of Complex CMOS Gates. PATMOS (2005)
José Luis Rosselló, Carol de Benito, Jaume Segura
A compact gate-level energy and delay model of dynamic CMOS gates. IEEE Trans. Circuits Syst. II Express Briefs (10) (2005)
José Luis Rosselló, Vicent Canals, Sebastià A. Bota, Ali Keshavarzi, Jaume Segura
A Fast Concurrent Power-Thermal Model for Sub-100nm Digital ICs. DATE (2005)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura
Smart Temperature Sensor for Thermal Testing of Cell-Based ICs. DATE (2005)
José Luis Rosselló, Jaume A. Segura
An analytical charge-based compact delay model for submicrometer CMOS inverters. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2004)
Sebastià A. Bota, M. Rosales, José Luis Rosselló, Jaume Segura, Ali Keshavarzi
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism. ITC (2004)
José Luis Rosselló, Jaume Segura
A Compact Propagation Delay Model for Deep-Submicron CMOS Gates including Crosstalk. DATE (2004)
Josep Altet, Antonio J. Rubio, José Luis Rosselló, Jaume Segura
Structural RFIC device testing through built-in thermal monitoring. IEEE Commun. Mag. 41 (9) (2003)
José Luis Rosselló, Jaume Segura
A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates. PATMOS (2003)
José Luis Rosselló, Jaume Segura
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers. PATMOS (2002)
José Luis Rosselló, Jaume Segura
Charge-based analytical model for the evaluation of powerconsumption in submicron CMOS buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
José Luis Rosselló, Jaume Segura
Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization. ICCAD (2001)
Jaume Segura, José Luis Rosselló, J. Morra, H. Sigg
A variable threshold voltage inverter for CMOS programmable logic circuits. IEEE J. Solid State Circuits 33 (8) (1998)