Ivan de Paúl

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 4

Top Topics

Delay Insensitive

Power Consumption

Fully Integrated

Top Venues

Publications

Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, Sebastia Bota, Jaume Segura
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results. CoRR (2024)
Sebastià A. Bota, Salvador Barcelo, Gabriel Torrens, Rafel Perelló, Jaume Verd, Ivan de Paúl, Jaume Segura
A Compact Double-Exponential Circuit for Single Event Transient Emulation. DCIS (2023)
Rafel Perelló-Roig, Francisca Orvay, Ivan de Paúl, Jaume Verd, Sebastià A. Bota, Jaume Segura
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring. IEEE SENSORS (2022)
Joan Barceló, Ivan de Paúl, Sebastià A. Bota, Jaume Segura, Jaume Verd
Bistability in a CMOS-MEMS Thermally Tuned Microbeam Resonator. ISCAS (2018)
Sebastià A. Bota, Gabriel Torrens, Ivan de Paúl, Bartomeu Alorda, L. A. Segura
Accurate alpha soft error rate evaluation in SRAM memories. IOLTS (2013)
José Luis Rosselló, Ivan de Paúl, Vincent Canals, Antoni Morro
Spiking Neural Network Self-configuration for Temporal Pattern Recognition Analysis. ICANN (1) (2009)
José Luis Rosselló, Vincent Canals, Antoni Morro, Ivan de Paúl
Practical Hardware Implementation of Self-configuring Neural Networks. ISNN (3) (2009)
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Sebastià A. Bota, Antoni Morro
A simple CMOS chaotic integrated circuit. IEICE Electron. Express 5 (24) (2008)
José Luis Rosselló, Vincent Canals, Ivan de Paúl, Jaume Segura
Using stochastic logic for efficient pattern recognition analysis. IJCNN (2008)
José Luis Rosselló, Ivan de Paúl, Vincent Canals
Self-configuring spiking neural networks. IEICE Electron. Express 5 (22) (2008)
Bartomeu Alorda, Ivan de Paúl, Jaume Segura
Charge-based testing BIST for embedded memories. IET Comput. Digit. Tech. 1 (5) (2007)
José Luis Rosselló, Sebastià A. Bota, Vicent Canals, Ivan de Paúl, Jaume Segura
A Fully CMOS Low-Cost Chaotic Neural Network. IJCNN (2006)
Bartomeu Alorda, Vicent Canals, Ivan de Paúl, Jaume Segura
A BIST-based Charge Analysis for Embedded Memories. IOLTS (2004)
Ivan de Paúl, Miquel Roca, Oscar Calvo, Raul Velazco
SEU fault injection in simulation environments: example of VHDL configuration on FPGA device. LATW (2002)
Ivan de Paúl, M. Rosales, Bartomeu Alorda, Jaume Segura, Charles F. Hawkins, Jerry M. Soden
Defect Oriented Fault Diagnosis for Semiconductor Memories using Charge Analysis: Theory and Experiments. VTS (2001)
Bartomeu Alorda, Ivan de Paúl, Jaume Segura, T. Miller
On-Line Current Testing for a Microprocessor Based Application with an Off-Chip Sensor. IOLTW (2000)