Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optimization.
José Luis RossellóJaume SeguraPublished in: ICCAD (2001)
Keyphrases
- power dissipation
- power consumption
- logic circuits
- high speed
- low power
- chip design
- circuit design
- cmos technology
- analog vlsi
- optimization algorithm
- power reduction
- dynamic optimization
- delay insensitive
- dynamic environments
- vlsi circuits
- power management
- optimization problems
- optimization process
- optimization method
- digital signal processing
- global optimization
- low cost
- single phase
- low voltage
- constrained optimization
- duty cycle