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Design-for-Test Techniques for Opens in Undetected Branches in CMOS Latches and Flip-Flops.
Antonio Zenteno Ramírez
Guillermo Espinosa
Víctor H. Champac
Published in:
IEEE Trans. Very Large Scale Integr. Syst. (2007)
Keyphrases
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case study
design process
high speed
power dissipation
user interface
real time
neural network
data model
signal to noise ratio
efficient implementation