Xuan-Tu Tran

Publication Activity (10 Years)

Years Active: 2006-2024
Publications (10 Years): 38

Top Topics

Hardware Architecture

High Efficiency

Spiking Neural Networks

Top Venues

Publications

Pham-Khoi Dong, Khanh N. Dang, Duy-Anh Nguyen, Xuan-Tu Tran
A light-weight neuromorphic controlling clock gating based multi-core cryptography platform. Microprocess. Microsystems 106 (2024)
Hiep Manh Dao, Vincent Beroulle, Yann Kieffer, Xuan-Tu Tran, Duy-Hieu Bui
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags. MCSoC (2023)
Ngo-Doanh Nguyen, Xuan-Tu Tran, Abderazek Ben Abdallah, Khanh N. Dang
An In-Situ Dynamic Quantization With 3D Stacking Synaptic Memory for Power-Aware Neuromorphic Architecture. IEEE Access 11 (2023)
Mohammed Omar Awadh Al-Shatari, Fawnizu Azmadi Hussin, Azrina Abd Aziz, Mohd Saufy Rohmad, Xuan-Tu Tran
Composite Lightweight Authenticated Encryption Based on LED Block Cipher and PHOTON Hash Function for IoT Devices. MCSoC (2022)
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
HotCluster: A Thermal-Aware Defect Recovery Method for Through-Silicon-Vias Toward Reliable 3-D ICs Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Hung K. Nguyen, Xuan-Tu Tran
Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator. ACM Trans. Parallel Comput. 9 (3) (2022)
Ngo-Doanh Nguyen, Duy-Hieu Bui, Fawnizu Azmadi Hussin, Xuan-Tu Tran
An Adaptive Hardware Architecture using Quantized HOG Features for Object Detection. ICICDT (2022)
Duy-Anh Nguyen, Xuan-Tu Tran, Francesca Iacopi
GAQ-SNN: A Genetic Algorithm based Quantization Framework for Deep Spiking Neural Networks. ICICDT (2022)
Duy-Anh Nguyen, Xuan-Tu Tran, Khanh N. Dang, Francesca Iacopi
A low-power, high-accuracy with fully on-chip ternary weight hardware architecture for Deep Spiking Neural Networks. Microprocess. Microsystems 90 (2022)
Khai-Duy Nguyen, Tuan-Kiet Dang, Trong-Thuc Hoang, Quynh Nguyen Quang Nhu, Xuan-Tu Tran, Cong-Kha Pham
A trigonometric hardware acceleration in 32-bit RISC-V microcontroller with custom instruction. IEICE Electron. Express 18 (16) (2021)
Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Khai-Duy Nguyen, Xuan-Tu Tran, Cong-Kha Pham
A proposal for enhancing training speed in deep learning models based on memory activity survey. IEICE Electron. Express 18 (15) (2021)
Marco Sarmiento, Khai-Duy Nguyen, Ckristian Duran, Trong-Thuc Hoang, Ronaldo Serrano, Van-Phuc Hoang, Xuan-Tu Tran, Koichiro Ishibashi, Cong-Kha Pham
A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 68 (9) (2021)
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
Report on power, thermal and reliability prediction for 3D Networks-on-Chip. CoRR (2020)
Khanh N. Dang, Michael Conrad Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip. IEEE Access 8 (2020)
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems. IEEE Access 8 (2020)
Duy-Anh Nguyen, Xuan-Tu Tran, Khanh N. Dang, Francesca Iacopi
A lightweight Max-Pooling method and architecture for Deep Spiking Convolutional Neural Networks. APCCAS (2020)
Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
A Lightweight AEAD encryption core to secure IoT applications. APCCAS (2020)
Mohammed Omar Awadh Al-Shatari, Fawnizu Azmadi Hussin, Azrina Abd Aziz, Gunawan Witjaksono, Xuan-Tu Tran
FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices. IEEE Access 8 (2020)
Xuan-Tu Tran, Ngoc-Sinh Nguyen, Duy-Hieu Bui, Minh-Trien Pham, Hung K. Nguyen, Cong-Kha Pham
Reducing Bitrate and Increasing the Quality of Inter Frame by Avoiding Quantization Errors in Stationary Blocks. EAI Endorsed Trans. Ind. Networks Intell. Syst. 7 (22) (2020)
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Pham-Khoi Dong, Hung K. Nguyen, Van-Phuc Hoang, Xuan-Tu Tran
Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture. APCCAS (2020)
Trong-Thuc Hoang, Ckristian Duran, Khai-Duy Nguyen, Tuan-Kiet Dang, Quynh Nguyen Quang Nhu, Phuc Hong Than, Xuan-Tu Tran, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham
Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB). IEICE Electron. Express 17 (20) (2020)
Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV Defects. ISVLSI (2019)
Duy-Anh Nguyen, Duy-Hieu Bui, Francesca Iacopi, Xuan-Tu Tran
An Efficient Event-driven Neuromorphic Architecture for Deep Spiking Neural Networks. SoCC (2019)
Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran
An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs. MCSoC (2019)
Pham-Khoi Dong, Hung K. Nguyen, Xuan-Tu Tran
A 45nm High-Throughput and Low Latency AES Encryption for Real-Time Applications. ISCIT (2019)
Khanh N. Dang, Michael Conrad Meyer, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran
2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults. APCCAS (2019)
Ngo-Doanh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization. APCCAS (2019)
Duy P. Nguyen, Xuan-Tu Tran, Nguyen L. K. Nguyen, Phat T. Nguyen, Anh-Vu Pham
A Wideband High Efficiency Ka-Band MMIC Power Amplifier for 5G Wireless Communications. ISCAS (2019)
Duy P. Nguyen, Xuan-Tu Tran, Phat T. Nguyen, Nguyen L. K. Nguyen, Anh-Vu Pham
High Gain High Efficiency Doherty Amplifiers with Optimized Driver Stages. MWSCAS (2019)
Hung K. Nguyen, Xuan-Tu Tran
A novel reconfigurable router for QoS guarantees in real-time NoC-based MPSoCs. J. Syst. Archit. 100 (2019)
Khanh N. Dang, Xuan-Tu Tran
Parity-Based ECC and Mechanism for Detecting and Correcting Soft Errors in On-Chip Communication. MCSoC (2018)
Hung K. Nguyen, Xuan-Tu Tran
A novel priority-driven arbiter for the router in reconfigurable Network-on-Chips. ICICDT (2018)
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. ICICDT (2017)
Xuan-Tu Tran, Tung Nguyen, Hai-Phong Phan, Duy-Hieu Bui
AXI-NoC: High-Performance Adaptation Unit for ARM Processors in Network-on-Chip Architectures. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2017)
Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah
A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model. IEEE Trans. Very Large Scale Integr. Syst. 25 (11) (2017)
Duy-Hieu Bui, Diego Puschini, Simone Bacles-Min, Edith Beigné, Xuan-Tu Tran
Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications. ICICDT (2016)
Khanh N. Dang, Michael Conrad Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran
Soft-error resilient 3D Network-on-Chip router. iCAST (2015)
Ngoc-Mai Nguyen, Edith Beigné, Suzanne Lesecq, Duy-Hieu Bui, Nam-Khanh Dang, Xuan-Tu Tran
H.264/AVC hardware encoders and low-power features. APCCAS (2014)
Ngoc-Sinh Nguyen, Duy-Hieu Bui, Xuan-Tu Tran
Reducing temporal redundancy in MJPEG using Zipfian estimation techniques. APCCAS (2014)
Ngoc-Mai Nguyen, Warody Lombardi, Edith Beigné, Suzanne Lesecq, Xuan-Tu Tran
FIFO-level-based power management and its application to an H.264 encoder. IECON (2014)
Nam-Khanh Dang, Xuan-Tu Tran, Alain Merirot
An efficient hardware architecture for inter-prediction in H.264/AVC encoders. DDECS (2014)
Tung Nguyen, Duy-Hieu Bui, Hai-Phong Phan, Trong-Trinh Dang, Xuan-Tu Tran
High-performance adaption of ARM processors into Network-on-Chip architectures. SoCC (2013)
Tien Van Do, Binh Thai Vu, Xuan-Tu Tran, Anh P. Nguyen
A generalized model for investigating scheduling schemes in computational clusters. Simul. Model. Pract. Theory 37 (2013)
Tran Van Hoang, Nguyen Ly Thien Truong, Hoang Trang, Xuan-Tu Tran
Design and Implementation of a SoPC System for Speech Recognition. MUE (2013)
Mai-Vu Tran, Duc-Trong Le, Xuan-Tu Tran, Tien-Tung Nguyen
A Model of Vietnamese Person Named Entity Question Answering System. PACLIC (2012)
Xuan-Tu Tran, Van-Huan Tran
Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders. DDECS (2011)
Mai-Vu Tran, Xuan-Tu Tran, Huy-Long Uong
User Interest Analysis with Hidden Topic in News Recommendation System. IALP (2010)
Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
Design-for-test approach of an asynchronous network-on-chip architecture and its associated test pattern generation and application. IET Comput. Digit. Tech. 3 (5) (2009)
Edith Beigné, Fabien Clermidy, Hélène Lhermet, Sylvain Miermont, Yvain Thonnart, Xuan-Tu Tran, Alexandre Valentian, Didier Varreau, Pascal Vivet, Xavier Popon, Hugo Lebreton
An Asynchronous Power Aware and Adaptive NoC Based Circuit. IEEE J. Solid State Circuits 44 (4) (2009)
Xuan-Tu Tran, Yvain Thonnart, Jean Durupt, Vincent Beroulle, Chantal Robach
A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application. NOCS (2008)
Xuan-Tu Tran, Jean Durupt, Yvain Thonnart, François Bertrand, Vincent Beroulle, Chantal Robach
Implementation of a Design-for-Test Architecture for Asynchronous Networks-on-Chip. NOCS (2007)
Xuan-Tu Tran, Vincent Beroulle, Jean Durupt, Chantal Robach, François Bertrand
Design-for-Test of Asynchronous Networks-on-Chip. DDECS (2006)
Xuan-Tu Tran, Jean Durupt, François Bertrand, Vincent Beroulle, Chantal Robach
A DFT Architecture for Asynchronous Networks-on-Chip. ETS (2006)