Low-Power Implementation of a High-Throughput Multi-core AES Encryption Architecture.
Pham-Khoi DongHung K. NguyenVan-Phuc HoangXuan-Tu TranPublished in: APCCAS (2020)
Keyphrases
- high throughput
- low power
- vlsi architecture
- cmos technology
- power consumption
- high speed
- low cost
- advanced encryption standard
- microarray
- genome wide
- signal processor
- biological data
- data acquisition
- systems biology
- single chip
- vlsi implementation
- logic circuits
- mixed signal
- encryption algorithms
- ultra low power
- nm technology
- secret key
- protein protein interactions
- proteomic data
- cryptographic algorithms
- encryption algorithm
- hardware implementation
- low power consumption
- real time
- power reduction
- encryption scheme
- digital signal processing
- image sensor
- mass spectrometry data
- genomic data
- gate array
- mass spectrometry
- power dissipation
- smart card
- gene expression
- data collection
- design considerations
- signal processing