Tomohiro Yoneda

Publication Activity (10 Years)

Years Active: 1985-2023
Publications (10 Years): 14

Top Topics

Run Length Encoding

Delay Insensitive

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

Publications

Yuji Yamada, Nesrine Berjab, Tomohiro Yoneda, Kenji Kise
A remote partial-reconfigurable SoC with a RISC-V soft processor targeting low-end FPGAs. MCSoC (2023)
Tomohiro Yoneda, Masashi Imai
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC (2020)
Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. 2019 (2019)
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC (2019)
Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82 (2018)
Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC (2018)
Hai-Phong Phan, Xuan-Tu Tran, Tomohiro Yoneda
Power consumption estimation using VNOC2.0 simulator for a fuzzy-logic based low power Network-on-Chip. ICICDT (2017)
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC (2017)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
An improved fault-tolerant routing algorithm for a Network-on-Chip derived with formal analysis. Sci. Comput. Program. 118 (2016)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS (2016)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC (2016)
Sarat Yoowattana, Tomohiro Yoneda
Improvement of Line Coding Overhead Targeting Both Run-Length and DC-Balance. MCSoC (2016)
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS (2016)
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
Dependable real-time task execution scheme for a many-core platform. DFTS (2015)
Masashi Imai, Tomohiro Yoneda
Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Tomohiro Yoneda, Masashi Imai
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD (2015)
Masashi Imai, Tomohiro Yoneda
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS (2014)
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. (6) (2014)
Zhen Zhang, Wendelin Serwe, Jian Wu, Tomohiro Yoneda, Hao Zheng, Chris J. Myers
Formal Analysis of a Fault-Tolerant Routing Algorithm for a Network-on-Chip. FMICS (2014)
Masashi Imai, Tomohiro Yoneda
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS (2014)
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS (2014)
Masashi Imai, Tomohiro Yoneda
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. (9) (2013)
Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi
Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. 2013 (2013)
Masashi Imai, Tomohiro Yoneda
Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC (2012)
Tomohiro Yoneda, Masashi Imai
Dependable routing in multi-chip NoC platforms for automotive applications. DFT (2012)
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Multi-chip NoCs for Automotive Applications. PRDC (2012)
Hiroshi Saito, Tomohiro Yoneda, Yuichi Nakamura
An ILP-based Multiple Task Allocation Method for Fault Tolerance in Networks-on-Chip. MCSoC (2012)
Scott Little, David Walter, Chris J. Myers, Robert A. Thacker, Satish Batchu, Tomohiro Yoneda
Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (4) (2011)
Masashi Imai, Tomohiro Yoneda
Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC (2011)
Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano
A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) (2011)
Masashi Imai, Tomohiro Yoneda
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT (2011)
Kedar S. Namjoshi, Tomohiro Yoneda
Preface. Int. J. Found. Comput. Sci. 21 (2) (2010)
Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement. IEEE Trans. Computers 59 (4) (2010)
Chammika Mannakkara, Tomohiro Yoneda
Asynchronous Pipeline Controller Based on Early Acknowledgement Protocol. IEICE Trans. Inf. Syst. (8) (2010)
Hiroshi Saito, Naohiro Hamada, Tomohiro Yoneda, Takashi Nanya
A floorplan method for asynchronous circuits with bundled-data implementation on FPGAs. ISCAS (2010)
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
N-way ring and square arbiters. ICCD (2009)
Hao Zheng, Haiqiong Yao, Tomohiro Yoneda
Synchronization-Based Abstraction Refinement for Modular Verification of Asynchronous Designs. ISVLSI (2009)
Naohiro Hamada, Yuki Shiga, Takao Konishi, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data Implementation. IPSJ Trans. Syst. LSI Des. Methodol. 2 (2009)
Naohiro Hamada, Yuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD (2008)
Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
A Conservative Framework for Safety-Failure Checking. IEICE Trans. Inf. Syst. (3) (2008)
David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda
Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Chammika Mannakkara, Tomohiro Yoneda
Asynchronous pipeline controller based on early acknowledgement protocol. ACSD (2008)
Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Informaticae 88 (4) (2008)
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (3) (2007)
Tomohiro Yoneda, Chris J. Myers
Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Frédéric Béal, Tomohiro Yoneda, Chris J. Myers
Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD (2007)
David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC (2007)
Tomohiro Yoneda, Chris J. Myers
Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA (2006)
Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda
Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD (2006)
Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
Verification of timed circuits with failure-directed abstractions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (3) (2006)
Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya
ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT (2006)
Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Trans. Inf. Syst. (11) (2005)
Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Trans. Inf. Syst. (7) (2005)
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers
High Level Synthesis of Timed Asynchronous Circuits. ASYNC (2005)
Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA (2004)
Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC (2004)
Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda
Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA (2004)
Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda
Verification of Timed Circuits with Failure Directed Abstractions. ICCD (2003)
Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD (2003)
Tomohiro Yoneda, Eric Mercer, Chris Myers
Modular Synthesis of Timed Circuits Using Partial Order Reduction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2002)
Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers
Automatic Derivation of Timing Constraints by Failure Analysis. CAV (2002)
Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC (2002)
Eric Mercer, Chris J. Myers, Tomohiro Yoneda
Modular Synthesis of Timed Circuits using Partial Order Reduction. Electron. Notes Theor. Comput. Sci. 65 (6) (2002)
Bin Zhou, Tomohiro Yoneda, Chris J. Myers
Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium (2001)
Hiroshi Toshima, Tomohiro Yoneda
Efficient verification by exploiting symmetry and abstraction. Systems and Computers in Japan 32 (14) (2001)
Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda
Verification of asynchronous circuits based on zero-suppressed BDDs. Systems and Computers in Japan 32 (2) (2001)
Tomoya Kitai, Tomohiro Yoneda
Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. PRDC (2001)
Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff
Conformance and mirroring for timed asychronous circuits. ASP-DAC (2001)
Tomohiro Yoneda
VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. CAV (2000)
Märt Saarepera, Tomohiro Yoneda
A Self-Timed Implementation of Boolean Functions. ASYNC (1999)
Tomohiro Yoneda, Hiroshi Ryu
Timed Trace Theoretic Verification Using Partial Order Reduction. ASYNC (1999)
Tomohiro Yoneda
Verification of Abstracted Instruction Cache of TITAC2: A Case Study. VLSI (1999)
Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff
Verification of Bounded Delay Asynchronous Circuits with Timed Traces. AMAST (1998)
Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera
Verification of Parameterized Asynchronous Circuits: A Case Study. ACSD (1998)
Tomohiro Yoneda, Bernd-Holger Schlingloff
Efficient Verification of Parallel Real-Time Systems. Formal Methods Syst. Des. 11 (2) (1997)
Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya
Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28 (8-9) (1997)
Tomohiro Yoneda, Takashi Yoshikawa
Using partial orders for trace theoretic verification of asynchronous circuits. ASYNC (1996)
Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato
BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. FMCAD (1996)
Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke
Efficient Verification of Parallel Real-Time Systems. CAV (1993)
Tomohiro Yoneda, Yoshihiro Tohma, Yutaka Kondo
Acceleration of timing verification method based on time petri nets. Systems and Computers in Japan 22 (12) (1991)
Tomohiro Yoneda, Kazutoshi Nakade, Yoshihiro Tohma
A fast timing verification method based on the independence of units. FTCS (1989)
Tomohiro Yoneda, Takashi Suzuoka, Yoshihiro Tohma
Interrupt handling in the loosely synchronized TMR system. Systems and Computers in Japan 16 (5) (1985)