Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits.
Tomoya KitaiTomohiro YonedaPublished in: PRDC (2001)
Keyphrases
- partial order reduction
- model checking
- asynchronous circuits
- temporal logic
- formal verification
- petri net
- verification method
- concurrent systems
- structured data
- delay insensitive
- high speed
- formal methods
- logic synthesis
- relational databases
- databases
- digital circuits
- logic circuits
- model based diagnosis
- low cost
- computer vision
- data mining
- real world