A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits.
Tomohiro YonedaMasashi ImaiPublished in: ICCD (2015)
Keyphrases
- low power
- asynchronous circuits
- high speed
- delay insensitive
- low cost
- single chip
- low power consumption
- mixed signal
- power consumption
- cmos technology
- ultra low power
- image sensor
- power dissipation
- signal processor
- wireless transmission
- communication protocol
- nm technology
- high power
- logic circuits
- vlsi circuits
- communication networks
- vlsi architecture
- real time
- cmos image sensor
- model checking
- digital camera
- digital signal processing
- gate array
- power reduction