Masashi Imai

Publication Activity (10 Years)

Years Active: 1997-2021
Publications (10 Years): 14

Top Topics

Asynchronous Circuits

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEICE Trans. Inf. Syst.

Publications

Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara
An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. GCCE (2021)
Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. IEICE Electron. Express 17 (14) (2020)
Tomohiro Yoneda, Masashi Imai
Coarse Grained versus Fine Grained Architectures for Asynchronous Reconfigurable Devices. ASYNC (2020)
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. MWSCAS (2019)
Tomohiro Yoneda, Peter A. Beerel, Alex Yakovlev, Masashi Imai
Asynchronous Circuit Design and its Applications: Past, Present and Future (NII Shonan Meeting 133). NII Shonan Meet. Rep. 2019 (2019)
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC (2019)
Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
MTJ-based asynchronous circuits for Re-initialization free computing against power failures. Microelectron. J. 82 (2018)
Masashi Imai, Shinichiro Akasaka, Tomohiro Yoneda
Novel Delay Elements for Bundled-Data Transfer Circuits Based on Two-Phase Handshaking Protocols. ASYNC (2018)
Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. ISQED (2017)
Naoya Onizawa, Masashi Imai, Takahiro Hanyu, Tomohiro Yoneda
MTJ-based Asynchronous Circuits for Re-initialization Free Computing against Power Failures. ASYNC (2017)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
Task Scheduling Based Redundant Task Allocation Method for the Multi-Core Systems with the DTTR Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2017)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
A task allocation method for the DTTR scheme based on task scheduling of fault patterns. ISCAS (2016)
Hiroshi Saito, Masashi Imai, Tomohiro Yoneda
A Task Allocation Method for the DTTR Scheme Based on the Parallelism of Tasks. MCSoC (2016)
Masashi Imai, Thiem Van Chu, Kenji Kise, Tomohiro Yoneda
The synchronous vs. asynchronous NoC routers: an apple-to-apple comparison between synchronous and transition signaling asynchronous designs. NOCS (2016)
Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. ISQED (2015)
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Kenji Kise
Dependable real-time task execution scheme for a many-core platform. DFTS (2015)
Masashi Imai, Tomohiro Yoneda
Novel Implementation Method of Multiple-Way Asynchronous Arbiters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2015)
Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
Signal Propagation Delay Model in Vertically Stacked Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Tomohiro Yoneda, Masashi Imai
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits. ICCD (2015)
Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa
Clock skew reduction for stacked chips using multiple source buffers. ISCIT (2015)
Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa
Modeling of substrate contacts in TSV-based 3D ICs. 3DIC (2014)
Masashi Imai, Tomohiro Yoneda
Energy-and-performance efficient differential domino logic cell libraries for QDI-model-based asynchronous circuits. APCCAS (2014)
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. (6) (2014)
Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
Effect of substrate contacts on reducing crosstalk noise between TSVs. APCCAS (2014)
Masashi Imai, Tomohiro Yoneda
Multiple-clock multiple-edge-triggered multiple-bit flip-flops for two-phase handshaking asynchronous circuits. ISCAS (2014)
Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa
Impact of on-chip interconnects on vertical signal propagation in 3D ICs. APCCAS (2014)
Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura
An NoC-based evaluation platform for safety-critical automotive applications. APCCAS (2014)
Masashi Imai, Tomohiro Yoneda
Fault Diagnosis and Reconfiguration Method for Network-on-Chip Based Multiple Processor Systems with Restricted Private Memories. IEICE Trans. Inf. Syst. (9) (2013)
Masashi Imai, Tomohiro Yoneda
Performance Modeling and Analysis of On-chip Networks for Real-Time Applications. PRDC (2012)
Tomohiro Yoneda, Masashi Imai
Dependable routing in multi-chip NoC platforms for automotive applications. DFT (2012)
Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu
Multi-chip NoCs for Automotive Applications. PRDC (2012)
Masashi Imai, Tomohiro Yoneda
Improving Dependability and Performance of Fully Asynchronous On-chip Networks. ASYNC (2011)
Masashi Imai, Tomohiro Yoneda
Duplicated Execution Method for NoC-based Multiple Processor Systems with Restricted Private Memories. DFT (2011)
Masashi Imai, Tomohide Nagai, Takashi Nanya
Pair and swap: An approach to graceful degradation for dependable chip multiprocessors. DSN Workshops (2010)
James L. Weston, Masashi Imai, Tomohide Nagai, Takashi Nanya
An Efficient Decision Unit for the Pair and Swap Methodology within Chip Multiprocessors. PRDC (2010)
Masashi Imai, Tomohiro Yoneda, Takashi Nanya
N-way ring and square arbiters. ICCD (2009)
Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design (2009)
Masashi Imai, Kouei Takada, Takashi Nanya
Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors. ASYNC (2009)
Masashi Imai, Takashi Nanya
A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries. ACSD (2008)
Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. DATE (2007)
Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Masashi Imai, Takashi Nanya
A Novel Design Method for Asynchronous Bundled-data Transfer Circuits Considering Characteristics of Delay Variations. ASYNC (2006)
Masashi Imai, Metehan Özcan, Takashi Nanya
Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. ASYNC (2004)
Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya
Skewed Checkpointing for Tolerating Multi-Node Failures. SRDS (2004)
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
Asynchronous Scan-Latch controller for Low Area Overhead DFT. ICCD (2004)
Nattha Sretasereekul, Hiroshi Saito, Masashi Imai, Euiseok Kim, Metehan Özcan, K. Thongnoo, Hiroshi Nakamura, Takashi Nanya
A zero-time-overhead asynchronous four-phase controller. ISCAS (5) (2003)
Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. ASYNC (2003)
Nattha Sretasereekul, Hiroshi Saito, Euiseok Kim, Metehan Özcan, Masashi Imai, Hiroshi Nakamura, Takashi Nanya
Synthesis of Serial Local Clock Controllers for Asynchronous Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Hiroshi Saito, Euiseok Kim, Masashi Imai, Nattha Sretasereekul, Hiroshi Nakamura, Takashi Nanya
Control signal sharing of asynchronous circuits using datapath delay information. ISCAS (5) (2003)
Masayuki Tsukisaka, Masashi Imai, Takashi Nanya
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS (2002)
T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. APCCAS (1) (2002)
Metehan Özcan, Masashi Imai, Takashi Nanya
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. ASYNC (2002)
Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. ASYNC (2001)
Akihiro Takamura, Motokazu Ozawa, Izumi Fukasaku, Taro Fujii, Yoichiro Ueno, Masashi Imai, Masashi Kuwako, Takashi Nanya
TITAC-2: An Asynchronous 32-bit Microprocessor. ASP-DAC (1998)
Akihiro Takamura, Masashi Kuwako, Masashi Imai, Taro Fujii, Motokazu Ozawa, Izumi Fukasaku, Yoichiro Ueno, Takashi Nanya
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model. ICCD (1997)