Fine-Grain Leakage Power Reduction Method for m-out-of-n Encoded Circuits Using Multi-threshold-Voltage Transistors.
Masashi ImaiKouei TakadaTakashi NanyaPublished in: ASYNC (2009)
Keyphrases
- reduction method
- fine grain
- coarse grain
- power consumption
- cmos technology
- low voltage
- parallel computation
- low power
- circuit design
- power dissipation
- field effect transistors
- selection algorithm
- nested transactions
- integrated circuit
- distributed memory
- multi dimensional
- multithreading
- computational power
- leaf nodes
- high density
- data management
- databases
- floating gate
- flip flops