Atsushi Kurokawa

Publication Activity (10 Years)

Years Active: 2003-2023
Publications (10 Years): 23

Top Topics

Countermeasures

Distribution Network

Top Venues

IEICE Electron. Express

Publications

Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
Bayesian neural network based inductance calculations of wireless power transfer systems. IEICE Electron. Express 20 (5) (2023)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A parabolic spiral coil transmitter with uniform magnetic field for smart devices. IEICE Electron. Express 20 (1) (2023)
Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa
Electronic component placement optimization for heat measures of smartglasses. IEICE Electron. Express 20 (6) (2023)
Taisei Arima, Shigeru Hidaka, Ryosuke Watanabe, Tomoya Akasaka, Atsushi Kurokawa, Toshiki Kanamoto
A thermally optimizing method of thin film resistor trimming with machine learning. IEICE Electron. Express 20 (5) (2023)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A bernoulli spiral coil transmitter for charging various small electronic devices. IEICE Electron. Express 19 (23) (2022)
Ryosuke Watanabe, Shigeru Hidaka, Tomoya Akasaka, Shota Kajiya, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto
Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules. MWSCAS (2022)
Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems. GCCE (2022)
Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
Receiver coil built into belt for heat dissipation of watch-type smart devices. IEICE Electron. Express 19 (3) (2022)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers. GCCE (2022)
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa
Effective methods to promote heat dissipation of wrist wearables. IEICE Electron. Express 18 (5) (2021)
Kan Hatakeyama, Seria Kasai, Masashi Imai, Atsushi Kurokawa, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara
An Energy Efficient Processor Applicable to Continuous SPO2 Monitoring. GCCE (2021)
Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
Thermal placement on PCB of components including 3D ICs. IEICE Electron. Express 17 (3) (2020)
Toshiki Kanamoto, Koki Kasai, Kan Hatakeyama, Atsushi Kurokawa, Tomoyuki Nagase, Masashi Imai
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis. IEICE Electron. Express 17 (14) (2020)
Kodai Matsuhashi, Toshiki Kanamoto, Atsushi Kurokawa
Thermal Model and Countermeasures for Future Smart Glasses. Sensors 20 (5) (2020)
Koutaro Hachiya, Atsushi Kurokawa
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation. DATE (2020)
Toshiki Kanamoto, Masami Fukushima, Koichi Kitagishi, Seijin Nakayama, Hideki Ishihara, Koki Kasai, Atsushi Kurokawa, Masashi Imai
A Single-Stage RISC-V Processor to Mitigate the Von Neumann Bottleneck. MWSCAS (2019)
Motoki Ishizaki, Atsushi Kurokawa
Power Transfer System Combining Wireless Resonators and Wired Three-Coil Repeater. ISCAS (2019)
Koutaro Inaba, Tomohiro Yoneda, Toshiki Kanamoto, Atsushi Kurokawa, Masashi Imai
Hardware Trojan Insertion and Detection in Asynchronous Circuits. ASYNC (2019)
Koutaro Hachiya, Atsushi Kurokawa
Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC. 3DIC (2019)
Motoki Ishizaki, Atsushi Kurokawa
Repeater Coil Connections for WPT System with Wired Three Coils. GCCE (2019)
Kodai Matsuhashi, Atsushi Kurokawa
Thermal Countermeasures of Glass Wearable Devices. ICCE-TW (2019)
Motoki Ishizaki, Atsushi Kurokawa
Advantages and Characteristics of a WPT System with a Resonant Wired-2-Coil Repeater. APWCS (2019)
Kaoru Furumi, Masashi Imai, Atsushi Kurokawa
Cooling architectures using thermal sidewalls, interchip plates, and bottom plate for 3D ICs. ISQED (2017)
Masayuki Watanabe, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
An effective model for evaluating vertical propagation delay in TSV-based 3-D ICs. ISQED (2015)
Toshiki Kanamoto, Takeichiro Akamine, Hiroaki Ammo, Takashi Hasegawa, Kouhei Shimizu, Yoshinori Kumano, Masaharu Kawano, Atsushi Kurokawa
Structure optimization for timing in nano scale FinFET. IEICE Electron. Express 12 (9) (2015)
Nanako Niioka, Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
Signal Propagation Delay Model in Vertically Stacked Chips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Nanako Niioka, Masashi Imai, Masa-Aki Fukase, Yuuki Miura, Kaoru Furumi, Atsushi Kurokawa
Clock skew reduction for stacked chips using multiple source buffers. ISCIT (2015)
Masayuki Watanabe, Masa-Aki Fukase, Masashi Imai, Nanako Niioka, Tetsuya Kobayashi, Rosely Karel, Atsushi Kurokawa
Modeling of substrate contacts in TSV-based 3D ICs. 3DIC (2014)
Li Ding, Zhangcai Huang, Atsushi Kurokawa, Jing Wang, Yasuaki Inoue
An Effective Model of the Overshooting Effect for Multiple-Input Gates in Nanometer Technologies. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2014)
Masayuki Watanabe, Rosely Karel, Nanako Niioka, Tetsuya Kobayashi, Masa-Aki Fukase, Masashi Imai, Atsushi Kurokawa
Effect of substrate contacts on reducing crosstalk noise between TSVs. APCCAS (2014)
Nanako Niioka, Masayuki Watanabe, Rosely Karel, Tetsuya Kobayashi, Masashi Imai, Masa-Aki Fukase, Atsushi Kurokawa
Impact of on-chip interconnects on vertical signal propagation in 3D ICs. APCCAS (2014)
Li Ding, Jing Wang, Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
An analytical model of the overshooting effect for multiple-input gates in nanometer technologies. ISCAS (2013)
Masa-Aki Fukase, Atsushi Kurokawa, Kouhei Ichinohe, Tatsuya Takaki
Optimum design of the execution stage of embedded processors. ISCIT (2012)
Li Ding, Zhangcai Huang, Minglu Jiang, Atsushi Kurokawa, Yasuaki Inoue
Modeling the Overshooting Effect of Multi-Input gate in Nanometer Technologies. J. Circuits Syst. Comput. 21 (6) (2012)
Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Qiang Li, Bin Lin, Yasuaki Inoue
A Non-Iterative Method for Calculating the Effective Capacitance of CMOS Gates with Interconnect Load Effect. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (5) (2011)
Masa-Aki Fukase, Harunobu Uchiumi, Kazuki Narita, Tatsuya Takaki, Naomichi Mimura, Kohei Ichinohe, Tomoaki Sato, Atsushi Kurokawa
Development of a next generation ubiquitous processor chip. ISPACS (2011)
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. (3) (2010)
Kazuyuki Ooya, Yuji Takashima, Atsushi Kurokawa
Simple Analytical Formulas for Estimating IR-Drops in an Early Design Stage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2010)
Yuji Takashima, Kazuyuki Ooya, Atsushi Kurokawa
Practical Redundant-Via Insertion Method Considering Manufacturing Variability and Reliability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Minglu Jiang, Zhangcai Huang, Atsushi Kurokawa, Shuai Fang, Yasuaki Inoue
Accurate Method for Calculating the Effective Capacitance with RC Loads Based on the Thevenin Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2009)
Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2009)
Atsushi Kurokawa, Hiroshi Fujita, Tetsuya Ibe
Prevention in a Chip of EMI Noise Caused by X'tal Oscillator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2008)
Zhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue
Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies. ASP-DAC (2007)
Zhangcai Huang, Atsushi Kurokawa, Yun Yang, Hong Yu, Yasuaki Inoue
Modeling the Influence of Input-to-Output Coupling Capacitance on CMOS Inverter Delay. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Atsushi Kurokawa, Hiroo Masuda, Junko Fujii, Toshinori Inoshita, Akira Kasebe, Zhangcai Huang, Yasuaki Inoue
Determination of Interconnect Structural Parameters for Best- and Worst-Case Delays. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Kenichi Shinkai, Masanori Hashimoto, Atsushi Kurokawa, Takao Onoye
A gate delay model focusing on current fluctuation over wide-range of process and environmental variability. ICCAD (2006)
Atsushi Kurokawa, Akira Kasebe, Toshiki Kanamoto, Yun Yang, Zhangcai Huang, Yasuaki Inoue, Hiroo Masuda
Formula-Based Method for Capacitance Extraction of Interconnects with Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue
Effective capacitance for gate delay with RC loads. ISCAS (3) (2005)
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2005)
Atsushi Kurokawa, Masaharu Yamamoto, Nobuto Ono, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
Capacitance and Yield Evaluations Using a 90-nm Process Technology Based on the Dense Power-Ground Interconnect Architecture. ISQED (2005)
Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda
Dummy Filling Methods for Reducing Interconnect Capacitance and Number of Fills. ISQED (2005)
Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao
Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Hiroo Masuda, Shin-ichi Ohkawa, Atsushi Kurokawa, Masakazu Aoki
Challenge: variability characterization and modeling for 65- to 90-nm processes. CICC (2005)
Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda
Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue
Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Zhangcai Huang, Atsushi Kurokawa, Yasuaki Inoue, Junfa Mao
A Novel Model for Computing the Effective Capacitance of CMOS Gates with Interconnect Loads. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (10) (2005)
Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda
DEPOGIT: dense power-ground interconnect architecture for physical design integrity. ASP-DAC (2004)
Atsushi Kurokawa, Toshiki Kanamoto, Akira Kasebe, Yasuaki Inoue, Hiroo Masuda
Efficient capacitance extraction method for interconnects with dummy fills. CICC (2004)
Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
Approximate formulae approach for efficient inductance extraction. ASP-DAC (2003)
Atsushi Kurokawa, Takashi Sato, Hiroo Masuda
Approximation Formula Approach for the Efficient Extraction of On-Chip Mutual Inductances. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC (2003)
Atsushi Kurokawa, Kotaro Hachiya, Takashi Sato, Kazuya Tokumasu, Hiroo Masuda
Fast On-Chip Inductance Extraction of VLSI Including Angled Interconnects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2003)