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Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew.

Zhangcai HuangAtsushi KurokawaJun PanYasuaki Inoue
Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2005)
Keyphrases
  • high speed
  • low power
  • neural network
  • data mining
  • computer vision
  • case study
  • bayesian networks
  • power consumption
  • modeling method
  • cmos technology
  • dynamic response
  • vlsi circuits