Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Takashi SatoToshiki KanamotoAtsushi KurokawaYoshiyuki KawakamiHiroki OkaTomoyasu KitauraHiroyuki KobayashiMasanori HashimotoPublished in: ASP-DAC (2003)
Keyphrases
- power dissipation
- high speed
- transmission line
- prediction accuracy
- power consumption
- prediction model
- chip design
- prediction algorithm
- real time
- low cost
- computationally efficient
- low power
- high quality
- power grid
- real world
- physical characteristics
- printed circuit boards
- image sensor
- parameter space
- programmable logic
- signal processing
- high accuracy
- phase locked loop