Koutaro Hachiya

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 13

Top Topics

Route Optimization

Assembly Process

Distribution Network

Top Venues

IEICE Electron. Express

Publications

Koutaro Hachiya
Measurement Point Selection Algorithms for Testing Power TSVs. 3DIC (2023)
Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
Bayesian neural network based inductance calculations of wireless power transfer systems. IEICE Electron. Express 20 (5) (2023)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A parabolic spiral coil transmitter with uniform magnetic field for smart devices. IEICE Electron. Express 20 (1) (2023)
Kyosuke Kusumi, Koutaro Hachiya, Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa
Electronic component placement optimization for heat measures of smartglasses. IEICE Electron. Express 20 (6) (2023)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A bernoulli spiral coil transmitter for charging various small electronic devices. IEICE Electron. Express 19 (23) (2022)
Kai Sato, Toshiki Kanamoto, Ryotaro Kudo, Koutaro Hachiya, Atsushi Kurokawa
Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems. GCCE (2022)
Shinsuke Kashiwazaki, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
Receiver coil built into belt for heat dissipation of watch-type smart devices. IEICE Electron. Express 19 (3) (2022)
Ryotaro Kudo, Koutaro Hachiya, Toshiki Kanamoto, Atsushi Kurokawa
A Parabolic Spiral Coil Transmitter for Charging Multiple Receivers. GCCE (2022)
Kodai Matsuhashi, Koutaro Hachiya, Toshiki Kanamoto, Shinsuke Kashiwazaki, Kyosuke Kusumi, Atsushi Kurokawa
Effective methods to promote heat dissipation of wrist wearables. IEICE Electron. Express 18 (5) (2021)
Yuuta Satomi, Koutaro Hachiya, Toshiki Kanamoto, Ryosuke Watanabe, Atsushi Kurokawa
Thermal placement on PCB of components including 3D ICs. IEICE Electron. Express 17 (3) (2020)
Koutaro Hachiya
A Method to Detect Open Defects in Wire Segments of On-Chip Power Grids. ATS (2020)
Koutaro Hachiya, Atsushi Kurokawa
Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability Cancellation. DATE (2020)
Koutaro Hachiya, Atsushi Kurokawa
Variability Cancellation to Improve Diagnostic Performance of Testing through Silicon Vias in Power Distribution Network of 3D-IC. 3DIC (2019)
Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto
Impact of Self-Heating in Wire Interconnection on Timing. IEICE Trans. Electron. (3) (2010)
Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto
An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Koutaro Hachiya, Takayuki Ohshima, Hidenari Nakashima, Masaaki Soda, Satoshi Goto
Fast Methods to Estimate Clock Jitter due to Power Supply Noise. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2007)
Koutaro Hachiya, Hiroyuki Kobayashi, Takaaki Okumura, Takashi Sato, Hiroki Oka
A Method to Derive SSO Design Rule Considering Jitter Constraint. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (4) (2006)
Toshiki Kanamoto, Shigekiyo Akutsu, Tamiyo Nakabayashi, Takahiro Ichinomiya, Koutaro Hachiya, Atsushi Kurokawa, Hiroshi Ishikawa, Sakae Muromoto, Hiroyuki Kobayashi, Masanori Hashimoto
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)
Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto
On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC (2005)
Achim Basermann, Uwe Jaekel, M. Nordhausen, Koutaro Hachiya
Parallel iterative solvers for sparse linear systems in circuit simulation. Future Gener. Comput. Syst. 21 (8) (2005)
Koutaro Hachiya, Toshiyuki Saito, Toshiyuki Nakata, Norio Tanabe
Enhancement of parallelism for tearing-based circuit simulation. ASP-DAC (1997)