Akira Mochizuki

Publication Activity (10 Years)

Years Active: 1992-2017
Publications (10 Years): 6

Top Topics

Highly Reliable

Computing Paradigm

Top Venues

IEICE Electron. Express

IEICE Trans. Inf. Syst.

Publications

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors. IEEE Trans. Emerg. Top. Comput. 5 (2) (2017)
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS (2016)
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery. NANOARCH (2015)
Akira Mochizuki, Naoto Yube, Takahiro Hanyu
Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor. IECON (2015)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC (2015)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE (2015)
Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu
Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip. IEICE Trans. Inf. Syst. (9) (2014)
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11 (10) (2014)
Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu
High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs. IEICE Trans. Inf. Syst. (6) (2014)
Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link. ISMVL (2014)
Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11 (3) (2014)
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11 (13) (2014)
Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu
Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link. APCCAS (2014)
Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu
Energy-aware current-mode inter-chip link for a dependable GALS NoC platform. ISCAS (2014)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10 (23) (2013)
Akira Mochizuki, Masatomo Miura, Takahiro Hanyu
High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction. ISMVL (2007)
Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto
Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL (2007)
Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry. IEICE Trans. Electron. (4) (2007)
Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu
Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic. IEICE Trans. Electron. (11) (2006)
Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu
Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits. ISMVL (2006)
Akira Mochizuki, Takahiro Hanyu
Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic. ISMVL (2006)
Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu
TMR-Based Logic-in-Memory Circuit for Low-Power VLSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2005)
Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic. J. Multiple Valued Log. Soft Comput. 11 (5-6) (2005)
Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu
Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders. ISMVL (2005)
Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu
Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding. ISMVL (2004)
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
Multiple-Valued Dynamic Source-Coupled Logic. ISMVL (2003)
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. ISMVL (1995)
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic. ISMVL (1994)
Masami Shinohara, Shinya Saida, Yutaka Shimizu, Akira Mochizuki, Kanehiro Sorimachi
Three-Dimensional Tactile Display by Multi-Stage Actuator. J. Robotics Mechatronics 4 (3) (1992)