Shoun Matsunaga

Publication Activity (10 Years)

Years Active: 2007-2015
Publications (10 Years): 0

Top Topics

Search Mechanism

Top Venues

IEICE Electron. Express

Publications

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE (2015)
Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme. IEICE Electron. Express 11 (10) (2014)
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure. ASYNC (2014)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2014)
Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme. IEICE Electron. Express 11 (3) (2014)
Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu
Soft-Delay-Error Evaluation in Content-Addressable Memory. ISMVL (2014)
Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu
Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM. NEWCAS (2014)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10 (7) (2013)
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC (2012)
Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture. VLSIC (2012)
Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism. ASYNC (2012)
Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu
Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction. NEWCAS (2012)
Shoun Matsunaga, Takahiro Hanyu
Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM. ISMVL (2012)
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL (2011)
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. DATE (2009)
Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu
Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic. ASP-DAC (2007)