Masanori Natsui

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 18

Top Topics

Frame Interpolation

Neighboring Blocks

Top Venues

IEEE J. Solid State Circuits

Publications

Ken Asano, Masanori Natsui, Takahiro Hanyu
Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network Hardware. IEICE Trans. Inf. Syst. 107 (8) (2024)
Ken Asano, Masanori Natsui, Takahiro Hanyu
Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. ICECS (2023)
Kaede Sakai, Masanori Natsui, Takahiro Hanyu
Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing. MWSCAS (2023)
Fangcen Zhong, Masanori Natsui, Takahiro Hanyu
High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control. ISCAS (2023)
Ken Asano, Masanori Natsui, Takahiro Hanyu
Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware. ISMVL (2023)
Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu
Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator. MWSCAS (2022)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56 (4) (2021)
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits (2020)
Tomoki Chiba, Masanori Natsui, Takahiro Hanyu
Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks. ISMVL (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC (2019)
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54 (11) (2019)
Hiroki Suda, Masanori Natsui, Takahiro Hanyu
Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction. ISMVL (2018)
Masanori Natsui, Tomoki Chiba, Takahiro Hanyu
Design of MTJ-Based nonvolatile logic gates for quantized neural networks. Microelectron. J. 82 (2018)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui
Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor. DATE (2017)
Naoto Sugaya, Masanori Natsui, Takahiro Hanyu
Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission. ISMVL (2016)
Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104 (10) (2016)
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design. ISCAS (2016)
Masanori Natsui, Naoto Sugaya, Takahiro Hanyu
A study of a top-down error correction technique using Recurrent-Neural-Network-based learning. NEWCAS (2016)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure. VLSIC (2015)
Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki
Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm. DATE (2015)
Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu
Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time. ISMVL (2015)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction. IEEE J. Solid State Circuits 50 (2) (2015)
Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure. IEICE Electron. Express 11 (13) (2014)
Masanori Natsui, Takahiro Hanyu
Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI. NEWCAS (2014)
Masanori Natsui, Takahiro Hanyu
Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors. ISMVL (2014)
Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI. ISCAS (2013)
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications. IEICE Electron. Express 10 (23) (2013)
Masanori Natsui, Takahiro Hanyu
Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices. J. Multiple Valued Log. Soft Comput. 21 (5-6) (2013)
Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu
Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications. ISMVL (2013)
Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating. ISSCC (2013)
Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme. ASP-DAC (2012)
Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique. J. Multiple Valued Log. Soft Comput. 19 (1-3) (2012)
Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu
Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA. MWSCAS (2012)
Youngkeun Kim, Masanori Natsui, Takahiro Hanyu
Variation-resilient current-mode logic circuit design using MTJ devices. ISCAS (2012)
Masanori Natsui, Takahiro Hanyu
Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system. NEWCAS (2012)
Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu
Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control. ISMVL (2012)
Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu
Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme. ISMVL (2011)
Takayuki Konishi, Kenji Inazu, Jun Gyu Lee, Masanori Natsui, Shoichi Masui, Boris Murmann
Lookup Table Methodology. IEICE Trans. Electron. (3) (2011)
Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu
Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme. IEICE Trans. Inf. Syst. (8) (2010)
Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu
Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control. ISMVL (2010)
Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. ISMVL (2009)
Masanori Natsui, Yoshiaki Tadokoro
Automated Sizing of Analog Circuits based on Genetic Algorithm with Parameter Orthogonalization Procedure. ICINCO-ICSO (2008)
Masanori Natsui, Yoshiaki Tadokoro, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. IEICE Electron. Express 4 (3) (2007)
Yoshiaki Tadokoro, Masanori Natsui, Yasuhiro Seto, Michiru Yamaguchi
Pitch estimation of difficult polyphony sounds overlapping some frequency components. ICINCO-SPSMC (2006)
Masanori Natsui, Shunichi Kubo, Yoshiaki Tadokoro
GA-based approach to pitch recognition of musical consonance. ICINCO-SPSMC (2006)
Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. J. Multiple Valued Log. Soft Comput. 11 (5-6) (2005)
Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN (2004)
Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation (2003)
Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. ISMVL (2002)
Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (9) (2002)
Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. ISMVL (2001)