A design method for 1-out-of-4 encoded low-power self-timed circuits using standard cell libraries.

Masashi Imai Takashi Nanya

Published in: ACSD (2008)

Keyphrases

low power
high speed
logic circuits
power consumption
single chip
low cost
design process
power reduction
power dissipation
cmos technology
vlsi architecture
wireless networks
digital signal processing
mixed signal
vlsi circuits