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Taro Fujii
Publication Activity (10 Years)
Years Active: 1997-2024
Publications (10 Years): 2
Top Topics
Embedded Systems
Pruning Method
Real Environment
Obstacle Avoidance
Top Venues
ISSCC
VLSI Circuits
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Publications
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Koichi Nose
,
Taro Fujii
,
Katsumi Togawa
,
Shunsuke Okumura
,
Kentaro Mikami
,
Daichi Hayashi
,
Teruhito Tanaka
,
Takao Toi
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications.
ISSCC
(2024)
Taro Fujii
,
Takao Toi
,
Teruhito Tanaka
,
Katsumi Togawa
,
Toshiro Kitaoka
,
Kengo Nishino
,
Noritsugu Nakamura
,
Hiroki Nakahara
,
Masato Motomura
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications.
VLSI Circuits
(2018)
Eric Shun Fukuda
,
Hideyuki Kawashima
,
Hiroaki Inoue
,
Taro Fujii
,
Koichiro Furuta
,
Tetsuya Asai
,
Masato Motomura
C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join.
ARC
(2013)
Takao Toi
,
Noritsugu Nakamura
,
Taro Fujii
,
Toshiro Kitaoka
,
Katsumi Togawa
,
Koichiro Furuta
,
Toru Awashima
Optimizing time and space multiplexed computation in a dynamically reconfigurable processor.
FPT
(2013)
Hideharu Amano
,
Takeshi Inuo
,
Hirokazu Kami
,
Taro Fujii
,
Masayasu Suzuki
Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases.
FPL
(2004)
Katsuhiro Honda
,
Nobuhiro Togo
,
Taro Fujii
,
Hidetomo Ichihashi
Linear fuzzy clustering based on least absolute deviations.
FUZZ-IEEE
(2002)
Koichiro Furuta
,
Taro Fujii
,
Masato Motomura
,
Kazutoshi Wakabayashi
,
Masakazu Yamashina
Spatial-temporal mapping of real applications on a Dynamically Reconfigurable Logic Engine (DRLE) LSI.
CICC
(2000)
Yuichiro Shibata
,
Masaki Uno
,
Hideharu Amano
,
Koichiro Furuta
,
Taro Fujii
,
Masato Motomura
A Virtual Hardware System on a Dynamically Reconfigurable Logic Device.
FCCM
(2000)
Akihiro Takamura
,
Motokazu Ozawa
,
Izumi Fukasaku
,
Taro Fujii
,
Yoichiro Ueno
,
Masashi Imai
,
Masashi Kuwako
,
Takashi Nanya
TITAC-2: An Asynchronous 32-bit Microprocessor.
ASP-DAC
(1998)
Akihiro Takamura
,
Masashi Kuwako
,
Masashi Imai
,
Taro Fujii
,
Motokazu Ozawa
,
Izumi Fukasaku
,
Yoichiro Ueno
,
Takashi Nanya
TITAC-2: An asynchronous 32-bit microprocessor based on Scalable-Delay-Insensitive model.
ICCD
(1997)