Shunsuke Okumura

Publication Activity (10 Years)

Years Active: 2008-2024
Publications (10 Years): 2

Top Topics

Dynamic Random Access Memory

Top Venues

IEICE Trans. Electron.

Publications

Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications. ISSCC (2024)
Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose
. VLSI Circuits (2019)
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. (4) (2014)
Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED (2014)
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC (2013)
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC (2013)
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Trans. Electron. (4) (2013)
Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2013)
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. (4) (2012)
Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto
Bit error rate estimation in SRAM considering temperature fluctuation. ISQED (2012)
Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9 (12) (2012)
Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED (2012)
Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. (4) (2012)
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5 (2012)
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. 7 (2) (2012)
Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. (10) (2012)
Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express 9 (6) (2012)
Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops (2012)
Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (8) (2012)
Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED (2012)
Shunsuke Okumura, Takuya Sawada, Paul H. Kyzivat
Session Initiation Protocol (SIP) Usage of the Offer/Answer Model. RFC 6337 (2011)
Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops (2011)
Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
. ESSCIRC (2011)
Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED (2011)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4 (2011)
Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6 (2) (2011)
Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi, Masahiko Yoshimoto
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC (2011)
Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS (2011)
Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi, Masahiko Yoshimoto
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED (2011)
Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi, Masahiko Yoshimoto
7T SRAM enabling low-energy simultaneous block copy. CICC (2010)
Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED (2010)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design (2009)
Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED (2009)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi, Masahiko Yoshimoto
A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. (4) (2009)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED (2008)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. (4) (2008)