256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V.
Jinwook JungYohei NakataShunsuke OkumuraHiroshi KawaguchiMasahiko YoshimotoPublished in: ICECS (2011)
Keyphrases
- knowledge base
- power reduction
- power consumption
- low cost
- reconfigurable architecture
- random access memory
- dynamic random access memory
- data transmission
- multithreading
- scheduling algorithm
- memory access
- multi objective evolutionary
- prefetching
- main memory
- general purpose
- hardware implementation
- query processing
- low power
- hit rate
- data access
- cache misses
- energy consumption
- back end
- cache management
- embedded processors
- caching scheme
- web caching
- digital signal
- multiple queries
- fine grain