Shinichi Moriwaki

Publication Activity (10 Years)

Years Active: 2010-2013
Publications (10 Years): 0

Top Topics

Power Consumption

Random Access Memory

Top Venues

IEEE J. Solid State Circuits

Publications

Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. IEEE J. Solid State Circuits 48 (4) (2013)
Shinichi Moriwaki, Yasuhiro Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Shinji Miyano, Takayasu Sakurai, Hirofumi Shinohara
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges. VLSIC (2012)
Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. ESSCIRC (2012)
Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED (2012)
Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano
0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC (2011)
Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme. A-SSCC (2011)
Toshikazu Suzuki, Shinichi Moriwaki, Atsushi Kawasumi, Shinji Miyano, Hirofumi Shinohara
0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme. ESSCIRC (2010)