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0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.

Shinichi MoriwakiAtsushi KawasumiToshikazu SuzukiTakayasu SakuraiShinji Miyano
Published in: CICC (2011)
Keyphrases
  • random access memory
  • data sets
  • line segments
  • protection scheme
  • hierarchical structure
  • edge detection
  • high speed
  • power consumption
  • data transmission
  • hash table
  • bit string
  • bit parallel