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0.5-V, 150-MHz, bulk-CMOS SRAM with suspended bit-line read scheme.
Toshikazu Suzuki
Shinichi Moriwaki
Atsushi Kawasumi
Shinji Miyano
Hirofumi Shinohara
Published in:
ESSCIRC (2010)
Keyphrases
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random access memory
power consumption
cmos technology
high speed
flip flops
nm technology
low power
low voltage
design considerations
power dissipation
protection scheme
low cost
line segments
main memory
power supply