A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells.
Shunsuke OkumuraShusuke YoshimotoHiroshi KawaguchiMasahiko YoshimotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2012)
Keyphrases
- random access memory
- low voltage
- cmos technology
- low power
- power consumption
- flip flops
- high density
- high speed
- low cost
- circuit design
- vlsi implementation
- design considerations
- power dissipation
- power reduction
- mixed signal
- nm technology
- single chip
- data transmission
- parallel processing
- load balancing
- memory access
- traffic load
- protection scheme
- embedded dram
- pseudorandom
- integrated circuit
- energy efficiency
- data access
- peak load