Koichi Nose

Publication Activity (10 Years)

Years Active: 1998-2024
Publications (10 Years): 4

Top Topics

Energy Dissipation

Emerging Technologies

Delay Insensitive

Top Venues

Publications

Koichi Nose, Taro Fujii, Katsumi Togawa, Shunsuke Okumura, Kentaro Mikami, Daichi Hayashi, Teruhito Tanaka, Takao Toi
20.3 A 23.9TOPS/W @ 0.8V, 130TOPS AI Accelerator with 16× Performance-Accelerable Pruning in 14nm Heterogeneous Embedded MPU for Real-Time Robot Applications. ISSCC (2024)
Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, Koichi Nose
. VLSI Circuits (2019)
Marian Verhelst, Dennis Sylvester, Makoto Takamiya, Mike Clinton, Kathy Wilcox, Koichi Nose
F4: Building the Internet of Everything (IoE): Low-power techniques at the circuit and system levels. ISSCC (2015)
Jan Genoe, Koichi Nose
Session 16 overview: Emerging technologies enabling next-generation systems: Technology directions subcommittee. ISSCC (2015)
Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits 47 (4) (2012)
Takashi Tokairin, Koichi Nose, Koichi Takeda, Koichiro Noguchi, Tadashi Maeda, Kazuyoshi Kawai, Masayuki Mizuno
A 280nW, 100kHz, 1-cycle start-up time, on-chip CMOS relaxation oscillator employing a feedforward period control scheme. VLSIC (2012)
Eisuke Saneyoshi, Koichi Nose, Masayuki Mizuno
A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect. ISSCC (2010)
Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45 (10) (2010)
Keishi Ohashi, Kenichi Nishi, Takanori Shimizu, Masafumi Nakada, Junichi Fujikata, Jun Ushida, Sunao Torii, Koichi Nose, Masayuki Mizuno, Hiroaki Yukawa, Masao Kinoshita, Nobuo Suzuki, Akiko Gomyo, Tsutomu Ishi, Daisuke Okamoto, Katsuya Furue, Toshihide Ueno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Jun Akedo
On-Chip Optical Interconnect. Proc. IEEE 97 (7) (2009)
Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC (2009)
Koichi Nose, Masayuki Mizuno
, 2.4 GHz RF Signal Quality Measurement Macro for RF Test and Diagnosis. IEEE J. Solid State Circuits 43 (4) (2008)
Junichi Fujikata, Kenichi Nishi, Akiko Gomyo, Jun Ushida, Tsutomu Ishi, Hiroaki Yukawa, Daisuke Okamoto, Masafumi Nakada, Takanori Shimizu, Masao Kinoshita, Koichi Nose, Masayuki Mizuno, Tai Tsuchizawa, Toshifumi Watanabe, Koji Yamada, Seiichi Itabashi, Keishi Ohashi
LSI On-Chip Optical Interconnection with Si Nano-Photonics. IEICE Trans. Electron. (2) (2008)
Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada
LAGS System Using Data/Instruction Grain Power Control. ISSCC (2007)
Toru Nakura, Koichi Nose, Masayuki Mizuno
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. ISSCC (2007)
Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC (2006)
Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits 41 (12) (2006)
Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. ISSCC (2006)
Hiroshi Kodama, Masayuki Mizuno, Koichi Nose, Akio Tanaka
Frequency-hopping vernier clock generators for multiple clock domain SoCs. CICC (2004)
Koichi Nose, Takayasu Sakurai
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED (2002)
Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
-hopping scheme to reduce subthreshold leakage for low-power processors. IEEE J. Solid State Circuits 37 (3) (2002)
Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi, Seongsoo Lee, Takayasu Sakurai
-hopping scheme for 82% power saving in low-voltage processors. CICC (2001)
Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED (2001)
Koichi Nose, Takayasu Sakurai
Analysis and future trend of short-circuit power. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (9) (2000)
Koichi Nose, Takayasu Sakurai
Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC (2000)
Koichi Nose, Soo-Ik Chae, Takayasu Sakurai
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED (2000)
Hiroshi Kawaguchi, Koichi Nose, Takayasu Sakurai
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits 35 (10) (2000)
Koichi Nose, Takayasu Sakurai
Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium (1998)