Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).
Koichi NoseSoo-Ik ChaeTakayasu SakuraiPublished in: ISLPED (2000)
Keyphrases
- power dissipation
- poster session
- digital circuits
- cmos technology
- low voltage
- finite state machines
- power consumption
- nm technology
- low power
- mixed signal
- circuit design
- digital signal processing
- data flow
- high speed
- student research workshop
- power management
- model checking
- model based diagnosis
- silicon on insulator
- reactive power
- machine learning
- power losses
- pattern matching
- low cost