Masahiro Nomura

Publication Activity (10 Years)

Years Active: 1990-2024
Publications (10 Years): 41

Top Topics

Gaussian Process

Evolution Strategy

Covariate Shift

Top Venues

GECCO Companion

Publications

Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa
CatCMA : Stochastic Optimization for Mixed-Category Problems. GECCO (2024)
Haruka Kiyohara, Masahiro Nomura, Yuta Saito
Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. CoRR (2024)
Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
CMA-ES for Safe Optimization. GECCO (2024)
Masahiro Nomura, Youhei Akimoto, Isao Ono
CMA-ES with Learning Rate Adaptation. CoRR (2024)
Haruka Kiyohara, Masahiro Nomura, Yuta Saito
Off-Policy Evaluation of Slate Bandit Policies via Optimizing Abstraction. WWW (2024)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
Marginal Probability-Based Integer Handling for CMA-ES Tackling Single- and Multi-Objective Mixed-Integer Black-Box Optimization. ACM Trans. Evol. Learn. Optim. 4 (2) (2024)
Yuta Saito, Masahiro Nomura
Hyperparameter Optimization Can Even be Harmful in Off-Policy Learning and How to Deal with It. CoRR (2024)
Kento Uchida, Ryoki Hamano, Masahiro Nomura, Shota Saito, Shinichi Shirakawa
CMA-ES for Safe Optimization. CoRR (2024)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Kento Uchida, Shinichi Shirakawa
CatCMA : Stochastic Optimization for Mixed-Category Problems. CoRR (2024)
Masahiro Nomura, Masashi Shibata
cmaes : A Simple yet Practical Python Library for CMA-ES. CoRR (2024)
Ryoki Hamano, Shinichi Shirakawa, Masahiro Nomura
Natural Gradient Interpretation of Rank-One Update in CMA-ES. CoRR (2024)
Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
Hot off the Press: Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. GECCO Companion (2024)
Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. CoRR (2023)
Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. CoRR (2023)
Masahiro Nomura, Youhei Akimoto, Isao Ono
CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? GECCO (2023)
Masahiro Nomura, Youhei Akimoto, Isao Ono
CMA-ES with Learning Rate Adaptation: Can CMA-ES with Default Population Size Solve Multimodal and Noisy Problems? CoRR (2023)
Yohei Watanabe, Kento Uchida, Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
(1+1)-CMA-ES with Margin for Discrete and Mixed-Integer Problems. GECCO (2023)
Shion Takeno, Masahiro Nomura, Masayuki Karasuyama
Towards Practical Preferential Bayesian Optimization with Skew Gaussian Processes. ICML (2023)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
CMA-ES with Margin for Single-and Multi-Objective Mixed-Integer Black-Box Optimization. CoRR (2022)
Masahiro Nomura, Isao Ono
Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. EvoApplications (2022)
Yoshihiko Ozaki, Yuki Tanigaki, Shuhei Watanabe, Masahiro Nomura, Masaki Onishi
Multiobjective Tree-Structured Parzen Estimator. J. Artif. Intell. Res. 73 (2022)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
Benchmarking CMA-ES with margin on the bbob-mixint testbed. GECCO Companion (2022)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
CMA-ES with margin: lower-bounding marginal probability for mixed-integer black-box optimization. GECCO (2022)
Masahiro Nomura, Isao Ono
Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CEC (2022)
Ryoki Hamano, Shota Saito, Masahiro Nomura, Shinichi Shirakawa
CMA-ES with Margin: Lower-Bounding Marginal Probability for Mixed-Integer Black-Box Optimization. CoRR (2022)
Masahiro Kato, Kaito Ariu, Masaaki Imaizumi, Masatoshi Uehara, Masahiro Nomura, Chao Qin
Optimal Fixed-Budget Best Arm Identification using the Augmented Inverse Probability Weighting Estimator in Two-Armed Gaussian Bandits with Unknown Variances. CoRR (2022)
Yuta Saito, Masahiro Nomura
Towards Resolving Propensity Contradiction in Offline Recommender Learning. IJCAI (2022)
Masahiro Nomura, Isao Ono
Fast Moving Natural Evolution Strategy for High-Dimensional Problems. CoRR (2022)
Masahiro Nomura, Isao Ono
Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. SSCI (2021)
Masahiro Nomura, Isao Ono
Natural Evolution Strategy for Unconstrained and Implicitly Constrained Problems with Ridge Structure. CoRR (2021)
Masahiro Nomura, Yuta Saito
Efficient Hyperparameter Optimization under Multi-Source Covariate Shift. CIKM (2021)
Masahiro Nomura, Nobuyuki Sakai, Nobusumi Fukushima, Isao Ono
Distance-weighted Exponential Natural Evolution Strategy for Implicitly Constrained Black-Box Function Optimization. CEC (2021)
Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi
Warm Starting CMA-ES for Hyperparameter Optimization. AAAI (2021)
Masahiro Nomura, Isao Ono
Towards a Principled Learning Rate Adaptation for Natural Evolution Strategies. CoRR (2021)
Masahiro Nomura, Shuhei Watanabe, Youhei Akimoto, Yoshihiko Ozaki, Masaki Onishi
Warm Starting CMA-ES for Hyperparameter Optimization. CoRR (2020)
Shintaro Takenaga, Shuhei Watanabe, Masahiro Nomura, Yoshihiko Ozaki, Masaki Onishi, Hitoshi Habe
Evaluating Initialization of Nelder-Mead Method for Hyperparameter Optimization in Deep Learning. ICPR (2020)
Masahiro Nomura, Yuta Saito
Multi-Source Unsupervised Hyperparameter Optimization. CoRR (2020)
Masahiro Nomura
Simple and Scalable Parallelized Bayesian Optimization. CoRR (2020)
Masahiro Nomura, Katsuhiro Nakamura
-EUC Security. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (1) (2019)
Masahiro Nomura
Heat Transfer in Nanostructured Si and Heat Flux Control Technique. 3DIC (2019)
Masahiro Nomura, Kenshi Abe
A Simple Heuristic for Bayesian Optimization with A Low Budget. CoRR (2019)
Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits. IEEE J. Solid State Circuits 49 (2) (2014)
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
-Aware Dual Supply Voltage Technique. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC (2013)
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Variation-aware subthreshold logic circuit design. ASICON (2013)
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits. IEEE J. Solid State Circuits 48 (8) (2013)
Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC (2012)
Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC (2012)
Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno
A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines. IEEE J. Solid State Circuits 47 (4) (2012)
Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. Circuits Syst. II Express Briefs (12) (2012)
Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai
limited ultra low voltage logic circuits. ISQED (2012)
Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
) of CMOS logic circuits with post-fabrication automatically selective charge injection. ISLPED (2011)
Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi
Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs. IEEE J. Solid State Circuits 46 (4) (2011)
Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
between flip-flops and combinational logics. ISLPED (2011)
Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
) of CMOS logic gates. DAC (2011)
Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED (2011)
Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. Circuits Syst. II Express Briefs (5) (2011)
Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC (2011)
Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai
Misleading energy and performance claims in sub/near threshold digital systems. ICCAD (2010)
Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara
A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations. IEEE J. Solid State Circuits 43 (4) (2008)
Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. ISSCC (2006)
Masahiro Nomura, Taku Ohsawa, Koichi Takeda, Yoetsu Nakazawa, Yoshinori Hirota, Yasuhiko Hagihara, Naoki Nishi
An Automatic Bi-Directional Bus Repeater Control Scheme Using Dynamic Collaborative Driving Techniques. IEICE Trans. Electron. (3) (2006)
Masahiro Nomura, Yoshifumi Ikenaga, Koichi Takeda, Yoetsu Nakazawa, Yoshiharu Aimoto, Yasuhiko Hagihara
Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes. IEEE J. Solid State Circuits 41 (4) (2006)
Koichi Takeda, Yasuhiko Hagihara, Yoshiharu Aimoto, Masahiro Nomura, Yoetsu Nakazawa, Toshio Ishii, Hiroyuki Kobatake
A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE J. Solid State Circuits 41 (1) (2006)
Kazumasa Suzuki, Masayuki Daito, Tomoo Inoue, Kouhei Nadehara, Masahiro Nomura, Masayuki Mizuno, Tomofumi Iima, Shoichiro Sato, Terumi Fukuda, Tomohisa Arai, Ichiro Kuroda, Masakazu Yamashina
A 2000-MOPS embedded RISC processor with a Rambus DRAM controller. IEEE J. Solid State Circuits 34 (7) (1999)
Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29 (3) (1994)
Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. IEEE J. Solid State Circuits 29 (12) (1994)
Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL (1990)