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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.

Ryo TakahashiHidehiro TakataTadashi YasufukuHiroshi FuketaMakoto TakamiyaMasahiro NomuraHirofumi ShinoharaTakayasu Sakurai
Published in: IEEE Trans. Circuits Syst. II Express Briefs (2012)
Keyphrases
  • logic circuits
  • power dissipation
  • cmos technology
  • low power
  • power consumption
  • tunnel diode
  • functional decomposition
  • high speed
  • gate array
  • low cost
  • digital signal processing
  • design methodology
  • logic synthesis