13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Koji HirairiYasuyuki OkumaHiroshi FuketaTadashi YasufukuMakoto TakamiyaMasahiro NomuraHirofumi ShinoharaTakayasu SakuraiPublished in: ISSCC (2012)
Keyphrases
- power reduction
- power consumption
- fully integrated
- low power
- power saving
- power dissipation
- cmos technology
- clock gating
- energy efficiency
- high speed
- low cost
- image sensor
- silicon on insulator
- metal oxide semiconductor
- digital signal processing
- workflow management
- multithreading
- real time
- energy saving
- computational power
- control strategy
- data center
- context aware
- image processing