Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Tadashi YasufukuSatoshi IidaHiroshi FuketaKoji HirairiMasahiro NomuraMakoto TakamiyaTakayasu SakuraiPublished in: ISLPED (2011)
Keyphrases
- low voltage
- logic circuits
- power supply
- clock gating
- cmos technology
- power consumption
- low power
- delay insensitive
- random access memory
- metal oxide
- high speed
- factors affecting
- factors that influence
- operating point
- chip design
- power system
- low cost
- metal oxide semiconductor
- silicon on insulator
- power dissipation
- design parameters
- multi valued
- logic programming
- solid state
- digital circuits
- circuit design
- analog vlsi
- minimum cost
- service quality
- asynchronous circuits
- digital forensics
- modal logic