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Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
Hiroshi Fuketa
Masahiro Nomura
Makoto Takamiya
Takayasu Sakurai
Published in:
IEEE J. Solid State Circuits (2014)
Keyphrases
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logic circuits
power dissipation
power reduction
power consumption
clock frequency
low power
cmos technology
power saving
energy efficiency
high speed
design methodology
data center
digital signal processing
low cost
processing units
parallel algorithm
data processing