Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.
Koichi TakedaToshio SaitoShinobu AsayamaYoshiharu AimotoHiroyuki KobatakeShinya ItoToshifumi TakahashiMasahiro NomuraKiyoshi TakeuchiYoshihiro HayashiPublished in: IEEE J. Solid State Circuits (2011)