Tadahiko Horiuchi

Publication Activity (10 Years)

Years Active: 1994-2002
Publications (10 Years): 0

Publications

Shinya Ito, Hiroaki Namba, Tsuyoshi Hirata, Koichi Ando, Shin Koyama, Nobuyuki Ikezawa, Tatsuya Suzuki, Takehiro Saitoh, Tadahiko Horiuchi
Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance. Microelectron. Reliab. 42 (2) (2002)
Koichiro Minami, Muneo Fukaishi, Masayuki Mizuno, Hideaki Onishi, Kenji Noda, Kiyotaka Imai, Tadahiko Horiuchi, Hiroshi Yamaguchi, Takanori Sato, Kazuyuki Nakamura, Masakazu Yaniashina
A 0.10 μm CMOS, 1.2 V, 2 GHz phase-locked loop with gain compensation VCO. CICC (2001)
Kenji Noda, Koichi Takeda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hideaki Kawamoto, Nobuyuki Ikezawa, Yoshiharu Aimoto, Noritsugu Nakamura, Takahiro Iwasaki, Hideo Toyoshima, Tadahiko Horiuchi
An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. IEEE J. Solid State Circuits 36 (3) (2001)
Koichi Takeda, Yoshiharu Aimoto, Noritsugu Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Kenji Noda, Koujirou Matsui, Shinya Itoh, Sadaaki Masuoka, Tadahiko Horiuchi, Atsushi Nakagawa, Kenju Shimogawa, Hiroyuki Takahashi
A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. IEEE J. Solid State Circuits 35 (11) (2000)
Kenji Noda, Koujirou Matsui, Shinya Ito, Sadaaki Masuoka, Hiroyuki Kawamoto, Nobuyuki Ikezawa, Koichi Takeda, Yoshiharu Aimoto, Naoto Nakamura, Hideo Toyoshima, Takahiro Iwasaki, Tadahiko Horiuchi
An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. CICC (2000)
Masanori Izumikawa, Hiroyuki Igura, Hitoshi Wakabayashi, Ken Nakajima, Tohru Mogami, Tadahiko Horiuchi, Masakazu Yamashina
A 0.25-μm CMOS 0.9-V 100-MHz DSP core. IEEE J. Solid State Circuits 32 (1) (1997)
Tomofumi lima, Masayuki Mizuno, Tadahiko Horiuchi, Masakazu Yamashina
Capacitance coupling immune, transient sensitive accelerator for resistive interconnect signals of subquarter micron ULSI. IEEE J. Solid State Circuits 31 (4) (1996)
Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. IEEE J. Solid State Circuits 29 (3) (1994)