An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield.
Kenji NodaKoujirou MatsuiShinya ItoSadaaki MasuokaHiroyuki KawamotoNobuyuki IkezawaKoichi TakedaYoshiharu AimotoNaoto NakamuraHideo ToyoshimaTakahiro IwasakiTadahiko HoriuchiPublished in: CICC (2000)
Keyphrases
- high speed
- high density
- low power
- magnetic tape
- random access memory
- high power
- low density
- close proximity
- shift register
- data center
- power consumption
- real time
- window search
- high bandwidth
- thin film
- data transmission
- data acquisition
- magnetic recording
- line segments
- design considerations
- frame rate
- high speed networks
- low voltage
- primal dual
- low latency
- power reduction
- steady state
- database