An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield.
Kenji NodaKoichi TakedaKoujirou MatsuiShinya ItoSadaaki MasuokaHideaki KawamotoNobuyuki IkezawaYoshiharu AimotoNoritsugu NakamuraTakahiro IwasakiHideo ToyoshimaTadahiko HoriuchiPublished in: IEEE J. Solid State Circuits (2001)