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Hachiro Yamada
Publication Activity (10 Years)
Years Active: 1994-1997
Publications (10 Years): 0
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Publications
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Yasuhiko Hagihara
,
Shigeto Inui
,
Fuyuki Okamoto
,
Masato Nishida
,
Toshihiko Nakamura
,
Hachiro Yamada
Floating-point datapaths with online built-in self speed test.
IEEE J. Solid State Circuits
32 (3) (1997)
Masayuki Mizuno
,
Masakazu Yamashina
,
Koichiro Furuta
,
Hiroyuki Igura
,
Hitoshi Abiko
,
Kazuhiro Okabe
,
Atsuki Ono
,
Hachiro Yamada
A GHz MOS adaptive pipeline technique using MOS current-mode logic.
IEEE J. Solid State Circuits
31 (6) (1996)
Tohru Miwa
,
Hachiro Yamada
,
Yoshinori Hirota
,
Toshiya Satoh
,
Hideki Hara
A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies.
IEEE J. Solid State Circuits
31 (11) (1996)
Masato Motomura
,
Toshiaki Inoue
,
Hachiro Yamada
,
Akihiko Konagaya
Cache-processor coupling: a fast and wide on-chip data cache design.
IEEE J. Solid State Circuits
30 (4) (1995)
Masahiro Nomura
,
Masakazu Yamashina
,
Junichi Goto
,
Toshiaki Inoue
,
Kazumasa Suzuki
,
Masato Motomura
,
Youichi Koseki
,
Benjamin S. Shih
,
Tadahiko Horiuchi
,
Nobuhisa Hamatake
,
Kouichi Kumagai
,
Tadayoshi Enomoto
,
Hachiro Yamada
A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI.
IEEE J. Solid State Circuits
29 (3) (1994)
Kazumasa Suzuki
,
Masakazu Yamashina
,
Takashi Nakayama
,
Masanori Izumikawa
,
Masahiro Nomura
,
Hiroyuki Igura
,
Hideki Heiuchi
,
Junichi Goto
,
Toshiaki Inoue
,
Youichi Koseki
,
Hitoshi Abiko
,
Kazuhiro Okabe
,
Atsuki Ono
,
Youich Yano
,
Hachiro Yamada
A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor.
IEEE J. Solid State Circuits
29 (12) (1994)