A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro.
Koichi TakedaYoshiharu AimotoNoritsugu NakamuraHideo ToyoshimaTakahiro IwasakiKenji NodaKoujirou MatsuiShinya ItohSadaaki MasuokaTadahiko HoriuchiAtsushi NakagawaKenju ShimogawaHiroyuki TakahashiPublished in: IEEE J. Solid State Circuits (2000)
Keyphrases
- low power
- cmos technology
- high speed
- power dissipation
- power consumption
- chip design
- nm technology
- low voltage
- leakage current
- low cost
- power reduction
- times faster
- vlsi circuits
- single chip
- digital signal processing
- image sensor
- cmos image sensor
- flip flops
- macroblock
- clock frequency
- random access memory
- real time
- neural network
- power line
- parallel processing
- finite state machines
- power management
- delay insensitive
- data acquisition
- rate distortion
- signal processing
- design considerations