Mikihiro Kajita

Publication Activity (10 Years)

Years Active: 2006-2011
Publications (10 Years): 0

Publications

Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests. IEICE Trans. Electron. (1) (2011)
Mikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto
Full Chip Circuit/Substrate Macro Modeling Method Which Controls the Analysis Accuracy and CPU Time by Using Current Density. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2010)
Mikiko Sode Tanaka, Mikihiro Kajita, Naoya Nakayama, Satoshi Nakamoto
A method using circuit/substrate macro modeling to analyze substrate noise in a 3.2-GHz 350M-transistor microprocessor. CICC (2008)
Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. ISSCC (2007)
Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. ISSCC (2006)
Koichi Nose, Mikihiro Kajita, Masayuki Mizuno
A 1-ps Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. IEEE J. Solid State Circuits 41 (12) (2006)