A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability.

Shunichi Kaeriyama Mikihiro Kajita Masayuki Mizuno

Published in: ISSCC (2007)

Keyphrases

high speed
low cost
power consumption
clock frequency
training set
data generator
test data
neural network
objective function
test cases
low power
high density
training phase
power dissipation
vlsi implementation
evolvable hardware