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A Clock Generator with Clock Period, Duty-Ratio and I/Q-Balance Adjustment Capabilities for On-Chip Timing-Margin Tests.
Shunichi Kaeriyama
Mikihiro Kajita
Masayuki Mizuno
Published in:
IEICE Trans. Electron. (2011)
Keyphrases
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high speed
power consumption
low cost
signal processing
standard deviation
asynchronous circuits
duty cycle