Yasuhiro Morita

Publication Activity (10 Years)

Years Active: 2005-2010
Publications (10 Years): 0

Publications

Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda
An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing. IEEE J. Solid State Circuits 45 (10) (2010)
Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Tadahiro Kuroda, Masayuki Mizuno
Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing. ISSCC (2009)
Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED (2008)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. (4) (2008)
Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16 (6) (2008)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Variation in Future Processes. IEICE Trans. Electron. (10) (2007)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI (2007)
Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Hideo Ohira, Masayuki Miyama, Masahiko Yoshimoto
A Feed-Forward Dynamic VDD-VBB-Frequency Management for Low Power Motion Video Compression on 90NM Risc Processor. Intell. Autom. Soft Comput. 12 (3) (2006)
Toshiyuki Miyamoto, Yasuhiro Morita, Sadatoshi Kumagai
Vertical Partitioning Method for Secret Sharing Distributed Database System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (11) (2006)
Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi, Masahiko Yoshimoto
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED (2006)
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto
-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2006)
Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto
Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2005)