Login / Signup

Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure.

Shusuke YoshimotoTakuro AmashitaShunsuke OkumuraHiroshi KawaguchiMasahiko Yoshimoto
Published in: IEICE Trans. Electron. (2012)
Keyphrases
  • random access memory
  • graph structure
  • bit vector
  • databases
  • digital images
  • tree structure
  • power consumption
  • database
  • genetic algorithm
  • hierarchical structure
  • design considerations
  • magnetic tape