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A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.

Masaharu TeradaShusuke YoshimotoShunsuke OkumuraToshikazu SuzukiShinji MiyanoHiroshi KawaguchiMasahiko Yoshimoto
Published in: ISQED (2012)
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