A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Masaharu TeradaShusuke YoshimotoShunsuke OkumuraToshikazu SuzukiShinji MiyanoHiroshi KawaguchiMasahiko YoshimotoPublished in: ISQED (2012)