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0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme.
Yohei Nakata
Shunsuke Okumura
Hiroshi Kawaguchi
Masahiko Yoshimoto
Published in:
Inf. Media Technol. (2012)
Keyphrases
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caching scheme
times faster
data access
management system
multithreading
memory hierarchy
query processing
power consumption
replacement policy
high speed
low power
parallel architecture
memory access
instruction set