A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
Yohei NakataYuta KimiShunsuke OkumuraJinwook JungTakuya SawadaTaku ToshikawaMakoto NagataHirofumi NakanoMakoto YabuuchiHidehiro FujiwaraKoji NiiHiroyuki KawaiHiroshi KawaguchiMasahiko YoshimotoPublished in: ISQED (2014)
Keyphrases
- memory subsystem
- random access memory
- failure rate
- main memory
- memory access
- processor core
- hash table
- multithreading
- dynamic random access memory
- memory hierarchy
- virtual memory
- cache conscious
- database management systems
- low cost
- upper bound
- lower bound
- data access
- cache misses
- feature selection
- embedded dram
- machine learning