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Yuta Kimi
Publication Activity (10 Years)
Years Active: 2014-2016
Publications (10 Years): 1
Top Topics
Cache Conscious
Dynamic Random Access Memory
Failure Rate
Low Latency
Top Venues
IEICE Trans. Electron.
ISQED
ATS
ARCS Workshops
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Publications
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Go Matsukawa
,
Yuta Kimi
,
Shuhei Yoshida
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
(6) (2016)
Yuta Kimi
,
Go Matsukawa
,
Shuhei Yoshida
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.
ATS
(2015)
Yuta Kimi
,
Go Matsukawa
,
Shuhei Yoshida
,
Shintaro Izumi
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
An accurate soft error propagation analysis technique considering temporal masking disablement.
IOLTS
(2015)
Go Matsukawa
,
Yohei Nakata
,
Yasuo Sugure
,
Shigeru Oho
,
Yuta Kimi
,
Masafumi Shimozawa
,
Shuhei Yoshida
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.
IEICE Trans. Electron.
(4) (2015)
Yohei Nakata
,
Yuta Kimi
,
Shunsuke Okumura
,
Jinwook Jung
,
Takuya Sawada
,
Taku Toshikawa
,
Makoto Nagata
,
Hirofumi Nakano
,
Makoto Yabuuchi
,
Hidehiro Fujiwara
,
Koji Nii
,
Hiroyuki Kawai
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation.
IEICE Trans. Electron.
(4) (2014)
Go Matsukawa
,
Yohei Nakata
,
Yuta Kimi
,
Yasuo Sugure
,
Masafumi Shimozawa
,
Shigeru Oho
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.
ARCS Workshops
(2014)
Yohei Nakata
,
Yuta Kimi
,
Shunsuke Okumura
,
Jinwook Jung
,
Takuya Sawada
,
Taku Toshikawa
,
Makoto Nagata
,
Hirofumi Nakano
,
Makoto Yabuuchi
,
Hidehiro Fujiwara
,
Koji Nii
,
Hiroyuki Kawai
,
Hiroshi Kawaguchi
,
Masahiko Yoshimoto
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement.
ISQED
(2014)