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A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.
Go Matsukawa
Yohei Nakata
Yasuo Sugure
Shigeru Oho
Yuta Kimi
Masafumi Shimozawa
Shuhei Yoshida
Hiroshi Kawaguchi
Masahiko Yoshimoto
Published in:
IEICE Trans. Electron. (2015)
Keyphrases
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low latency
real time
high speed
high bandwidth
high throughput
virtual machine
highly efficient
stream processing
continuous query processing
massive scale
xml documents
sliding window
data acquisition